Time-to-Digital Converters (TDCs) are used in many electronic circuits to estimate the time difference between two signals, e.g., a start signal and a stop signal, and to provide the time difference in digital form. One exemplary application for a TDC comprises a Radio Frequency (RF) circuit, where a TDC may be used to estimate the time difference between a reference signal and an oscillator signal in a Phase-Locked Loop (PLL) system. TDCs may also be used to detect light/photons in nuclear medical imaging, e.g., Positron Emission Tomography (PET), for Time-Of-Flight (TOF) measurements, e.g., in radiation detection and in laser radars, and in a variety of other space, nuclear, and measurement science applications.
Several types of TDCs exist in the literature. One type of TDC comprises a Charge-to-Digital Timer (CDT). The basic architecture for a conventional CDT comprises a current source, an integrator, and a flash analog-to-digital converter, such as disclosed in “Fast TDC for On-Line TOF Using Monolithic Flash A/D Converter,” J. Dawson, D. Underwood, IEEE Transactions on Nuclear Science, vol. NS-28, no. 1, February 1981. At the time of the Dawson et al. paper, the CDT was implemented using discrete components and a separate flash analog-to-digital converter.
Another exemplary TDC comprises a Vernier Delay Line (VDL), which uses a Complementary Metal-Oxide Semiconductor (CMOS) buffer/inverter delay to estimate the time difference between the start and stop signals. By using tapped delay lines, the TDC may achieve resolutions smaller than those achievable with a single inverter delay. For example, a VDL may achieve ˜20 ps resolution with a 65 nm CMOS process.
For cellular applications, target resolutions span from sub-picoseconds to tens of picoseconds. Even for the picosecond range resolution, the VDL solution requires some averaging or interpolation because the inverter speed and impedance mismatches limit the single-shot resolution to ˜10 ps. Thus, VDL solutions do not provide sufficient resolution for many cellular applications.
Further the tapped delay line of a VDL solution generally consumes a lot of power, especially when the start and/or stop signals are associated with a high clock frequency. Conventional solutions directed at reducing the power consumption of a VDL may cause power regulation problems in integrated solutions, non-linearities in the conversion, and/or performance degradations. In addition, it is difficult to characterize and calibrate the tapped delay line used in a VDL.
Thus, there remains a need for improved TDCs.